This chip, together with an IMXRT1062 microcontroller and Winbond flash memory allows you to create a DIY circuit board which is fully compatible with Teensy 4.0 or Teensy 4.1.

Supported Chips

An IMXRT microcontroller and flash memory chip must be paired with this MKL02 to form a working system. No programming or other setup is needed on these other chips. Blank chips sold by distributors are used.

IMXRT1062DV*6A (NXP)
W25Q16JV*IM (Winbond)
W25Q64JV*IM (Winbond)

IMXRT1062 chips with extended temperature range are likely to work, but have not been tested.

Winbond flash memory chips with a "Q" at the end of their part number do not work. Only the "M" parts are supported.

Power Up Sequence

The IMXRT1062 chip has special power-up sequence requirements. While PJRC generally recommends following the Teensy 4.0 or Teensy 4.1 schematic, understanding the proper power-up process is important for any design changes you may choose to make while designing your own PCB.

VIN / VUSB Power - Incoming power arrives at the USB voltage regulator build into the IMXRT chip, and the TLV75733P regulator.
USB_CAP & SNVS_IN - The USB voltage regulator turns on. VDD_USB_CAP charges up to approximately 2.5V. Because VDD_SNVS_IN is connected, the SNVS voltage regulator receives power.
SNVS_CAP - The SNVS voltage regulator turns on, creating 1.1V at VDD_SNVS_CAP.
NVCC_PLL & VDD_HIGH_CAP - The IMXRT power management system turns on the PLL and Analog regulators, creating 1.1V at NVCC_PLL and 2.5V at VDD_HIGH_CAP.
ON REQUEST - Once power is stable, PMIC_ON_REQ is driven high with 1.1V to request main power.
3.3V Power - The TLV75733P voltage regulator turns on, supplying the main 3.3V power to the entire board.
DCDC_PSWITCH - After 3.3V is stable for several milliseconds, the MKL02 chip drives DCDC_PSWITCH high.
CPU Power - The IMXRT DCDC buck converter begins producing 1.15V power for the CPU and most internal IMXRT circuitry. Later, software can adjust this voltage as needed for speeds greater than 528 MHz.

Power Design Notes

The built-in USB voltage regulator operates independently from the rest of the IMXRT power management. It may be powered up first, last, or at any time. USB power may also be removed and reapplied at any time without impacting the rest of the chip.

The SNVS voltage regulator must be powered up before any other on-chip regulators, except the USB regulator which is completely separate. The SNVS (Secure Non-Volatile Storage) system manages the power for the rest of the chip. If power is applied to the other regulators first, the IMXRT may fail to boot.

Before 3.3V power is applied, PMIC_ON_REQ is driven high with only 1.1V. The voltage regulator must be able to recognize 1.1V for proper startup. If a different voltage regulator is used, check its enable voltage threshold. Some chips require 1.5V or higher, which may not reliably start up.

If only 3.3V power is used, a solid state switch or P-channel mosfet should be used instead of the 3.3V regulator. For proper startup, 3.3V power to the IMXRT should be turned on when PMIC_ON_REQ is asserted.

PJRC does not recommend using a resistor-capacitor delay circuit to control DCDC_PSWITCH. This signal is not level sensitive. Simply being high will not enable the switching power supply. A low-to-high transition is required after 3.3V power is stable to cause the buck converted to start up.

Crystal Oscillator Guidelines

The 24 MHz crystal is required. As with all crystal oscillators, a solid ground plane should be routed on the PCB layer directly underneath the crystal. 2 capacitors and 1 resistor are required. See NXP's Hardware Development Guide for the MIMXRT1050/MIMXRT1060 Applications Processor, Rev.0, 08/2018 for details.

The 32.768 kHz crystal is optional. If not used, the IMXRT will automatically use a low accuracy 32 kHz internal oscillator.

Hardware Initialization

IMXRT fuses are initialized the first time the IMXRT1062 and MKL02 chip are used together. Bits 4 and 19 in the HW_OCOTP_CFG5 fuse word are set. Bit 4 allows booting from flash memory. Bit 19 configures IMXRT to communicate using JTAG.

The HW_OCOTP_MAC0 and HW_OCOTP_MAC1 fuses are also set with unique 48 bit Ethernet Mac address. Only a single IMXRT1062 may be initialized.

The first time the Program button is pressed, the top 4K of flash memory is written with a known-good LED blink program. When the program button is pressed for 15 seconds, the rest of the flash chip is erased and this LED blink is copied to the beginning of the flash memory. Because this copy is created on the first non-15-second press, the 15 second press for restore only works if a short press for normal bootloader entry has been done at least once.

Security Settings

The fuse settings are not locked, as they would be with a production Teensy 4.0 or Teensy 4.1. PJRC does not recommend setting any of the HW_OCOTP_CFG5 fuses. Altering these fuses could permanently "brick" your hardware.

TODO: program to lock fuse settings, to make hardware "unbrickable"

Currently the IMXRT authenication and encryption features are not supported. PJRC hopes to offer support for flash security with a future software update.

Troubleshooting & Diagnostic Blink Codes

If your custom board does not start up, first check the power supply. As described in the power supply startup sequence, the IMXRT internal voltage regulators must start first, then 3.3V power is turned on when PMIC_ON_REQ is driven high.

When the MKL02 chip receives stable 3.3V power, it will activate an internal pullup resistor on the Program signal (pin 10, PTB2). It will also drive DCDC_PSWITCH (connected to pin 3, PTA3) initially low and then high after 3.3V has remained stable for several milliseconds. This behavior on pin 3, PTA3 and the weak pullup in pin 10, PTB2 can confirm if the MKL02 has started properly.

If DCDC_PSWITCH has been driven high, the buck converter should develop 1.15 volts at VDD_SOC_IN. The processor and nearly all digital logic inside the IMXRT depends on proper VDD_SOC_IN power.

Once running, the MKL02 will blink its red LED when error conditions are detected. The blinks appear at 0.6 seconds apart and if the error condition remains, the pattern repeats after a 2 second pause.

2 Blinks = NXP JTAG Not Responding: No communication is working! The 2 likely causes for this problem are improper power startup sequence, or a problem with any of these connections between the MKL02 and IMXRT chip:
3 Blinks = Flash Chip Error, Missing or Incorrect ID: The flash memory chip did not respond to the JEDEC ID query, or it is an incompatible chip.
4 Blinks = ARM JTAG & SWD Not Responding (Needs Crystal): The NXP JTAG communication is working, but communication with ARM JTAG or SWD fails. Usually this error means the 24 MHz crystal is not oscillating. NXP's JTAG does not require the oscillator, but the ARM JTAG does. This error also be caused by a bad connection between PTB5 to AD_B0_08, which is the signal that selects which JTAG controller is accessible.
5 Blinks = Crystal Oscillator Is Unstable: The OSC_XTALOK (bit 15) flag in XTALOSC24M_MISC0 reported the 24 MHz crystal oscillator is not stable.
6 Blinks = reserved: This error is not used. It is reserved for future bootloader updates.
7 Blinks = ARM JTAG DAP Communication Error: A communication error was detected, but after correctly detecting (4 blinks) and initializing the ARM JTAG DAP (9 blinks). This error may indicate a severe signal quality problem or any of the signal wires shorted to other lines which are initially high impedance but become output after a program is running.
8 Blinks = Unknown IMXRT Chip: The IMXRT chip responded, but with an unsupported JTAG ID. This error can happen if IMXRT AD_BO_08 is not connected to MKL02 PTB5, or it is shorted to GND.
9 Blinks = ARM JTAG DAP Init Error: The ARM JTAG DAP was detected (4 blinks) but could not be initialized. This error is rather unlikely!
10 Blinks = Serial Number Already Assigned: A problem occurred with the serial number & ethernet mac address assignment.
11 Blinks = ARM SWD DAP Communication Error: An communication error was detected in the initial IMXRT fuses setup.
12 Blinks = Unable To Halt IMXRT: When attempting to enter bootloader mode, ARM JTAG communication is working (4, 7, 9 blinks) but the IMXRT M7 processor could not be halted to take control of the IMXRT chip.
13 Blinks = Unable To Access IMXRT Memory After CPU Halt: When attempting to enter bootloader mode, the IMXRT M7 processor was successfully halted (5, 7, 9, 12 blinks) but then memory could not be accessed. This error is extremely unlikely.