AT Attachment-3 Interface (ATA-3), Revision 6
1-3 Forward, Introduction, Scope,
Normative references, Definitions, abbreviations, and conventions
4 Interface physical and electrical requirements
5 Interface signal assignments and descriptions
6 Interface register definitions and descriptions
7 General operational requirements
8 Command descriptions
9 Protocol
10 Timing
Annex A Connectors
Annex B Identify device data for ATA devices
below 8 GB
Annex C Signal integrity
Annex D Bibliography
Annex E ATA command set summary
Detailed Contents
Foreword
Introduction
1 Scope
2 Normative references
3 Definitions, abbreviations, and conventions
3.1 Definitions and abbreviations
3.2 Conventions
3.2.1 Keywords
3.2.2 Numbering
3.2.3 Signal conventions
3.2.4 Bit conventions
3.2.5 Byte ordering for data transfers
4 Interface physical and electrical requirements
4.1 Cable configuration
4.2 I/O cable
4.3 Electrical characteristics
4.3.1 Driver types and required pull-ups
5 Interface signal assignments and descriptions
5.1 Signal summary
5.2 Signal descriptions
5.2.1 CS0- (CHIP SELECT 0)
5.2.2 CS1- (CHIP SELECT 1)
5.2.3 DA2, DA1, and DA0 (DEVICE ADDRESS)
5.2.4 DASP- (Device active, device 1 present)
5.2.5 DD (15:0) (Device data)
5.2.6 DIOR- (Device I/O read)
5.2.7 DIOW- (Device I/O write)
5.2.8 DMACK- (DMA acknowledge)
5.2.9 DMARQ (DMA request)
5.2.10 INTRQ (Device interrupt)
5.2.11 IOCS16- (Device 16-bit I/O)
5.2.12 IORDY (I/O channel ready)
5.2.13 PDIAG- (Passed diagnostics)
5.2.14 RESET- (Device reset)
5.2.15 CSEL (Cable select)
6 Interface register definitions and descriptions
6.1 Device addressing considerations
6.2 I/O register descriptions
6.2.1 Alternate Status register
6.2.2 Command register
6.2.3 Cylinder High register
6.2.4 Cylinder Low register
6.2.5 Data register
6.2.6 Data port
6.2.7 Device Control register
6.2.8 Device/Head register
6.2.9 Error register
6.2.10 Features register
6.2.11 Sector Count register
6.2.12 Sector Number register
6.2.13 Status register
7 General operational requirements
7.1 Reset response
7.2 Sector addressing
7.3 Power management feature set
7.3.1 Power modes
7.3.2 Power management commands
7.3.3 Standby timer
7.3.4 Idle mode transition
7.3.5 Status
7.3.6 Power mode transitions
7.4 Removable media mode transitions
7.5 Security mode feature set
7.5.1 Security mode default setting
7.5.2 Intial setting of the user password
7.5.3 Security mode operation from power-on
7.5.4 User password lost
7.6 Self-monitoring, analysis and reporting technology
7.6.1 Attributes
7.6.2 Attribute values
7.6.3 Attribute thresholds
7.6.4 Threshold exceeded condition
7.6.5 SMART commands
7.6.6 SMART operation with power management modes
8 Command descriptions
8.1 CHECK POWER MODE
8.2 DOOR LOCK
8.3 DOOR UNLOCK
8.4 DOWNLOAD MICROCODE
8.5 EXECUTE DEVICE DIAGNOSTIC
8.6 FORMAT TRACK
8.7 IDENTIFY DEVICE
8.7.1 Word 0: General configuration
8.7.2 Word 1: Number of cylinders
8.7.3 Word 2: Reserved.
8.7.4 Word 3: Number of logical heads
8.7.5 Word 4: Vendor specific data.
8.7.6 Word 5: Vendor specific data.
8.7.7 Word 6: Number of logical sectors per logical track
8.7.8 Words 7-9: Vendor specific data.
8.7.9 Words 10-19: Serial number
8.7.10 Word 20: Vendor specific data.
8.7.11 Word 21: Vendor specific data.
8.7.12 Word 22: Number of vendor specific bytes on READ/WRITE LONG commands
8.7.13 Word 23-26: Firmware revision
8.7.14 Words 27-46: Model number
8.7.15 Word 47: READ/WRITE MULTIPLE support.
8.7.16 Word 48: Reserved.
8.7.17 Word 49: Capabilities
8.7.17.1 Standby timer support
8.7.17.2 IORDY support
8.7.17.3 IORDY can be disabled
8.7.17.4 Obsolete
8.7.18 Word 50: Reserved
8.7.19 Word 51: PIO data transfer cycle timing mode
8.7.20 Word 52: Obsolete
8.7.21 Word 53: Field validity
8.7.22 Word 54: Number of current logical cylinders
8.7.23 Word 55: Number of current logical heads
8.7.24 Word 56: Number of current logical sectors per logical track
8.7.25 Word 57-58: Current capacity in sectors
8.7.26 Word 59: Multiple sector setting
8.7.27 Word 60-61: Total number of user addressable sectors
8.7.28 Word 62:Obsolete
8.7.29 Word 63: Multiword DMA transfer
8.7.30 Word 64: Flow control PIO transfer modes supported
8.7.31 Word 65: Minimum multiword DMA transfer cycle time per word
8.7.32 Word 66: Device recommended multiword DMA cycle time
8.7.33 Word 67: Minimum PIO transfer cycle time without flow control
8.7.34 Word 68: Minimum PIO transfer cycle time with IORDY
8.7.35 Words 69-79: Reserved
8.7.36 Word80: Major version number
8.7.37 Word81: Minor version number
8.7.38 Words 82-83: Command sets supported
8.7.39 Words 84-127: Reserved.
8.7.40 Word 128: Security status
8.7.40.1 Security count expired
8.7.40.2 Security level
8.7.40.3 Security frozen
8.7.40.4 Security locked
8.7.40.5 Security enabled
8.7.40.6 Security supported
8.7.41 Words 129-159: Vendor specific.
8.7.42 Words 160-255: Reserved.
8.8 IDENTIFY DEVICE DMA
8.9 IDLE
8.10 IDLE IMMEDIATE
8.11 INITIALIZE DEVICE PARAMETERS
8.12 MEDIA EJECT
8.13 NOP
8.14 READ BUFFER
8.15 READ DMA (with retries and without retries)
8.16 READ LONG (with retries and without retries)
8.17 READ MULTIPLE
8.18 READ SECTOR(S) (with retries and without retries)
8.19 READ VERIFY SECTOR(S) (with retries and without retries)
8.20 RECALIBRATE
8.21 SECURITY DISABLE PASSWORD
8.22 SECURITY ERASE PREPARE
8.23 SECURITY ERASE UNIT
8.24 SECURITY FREEZE LOCK
8.25 SECURITY SET PASSWORD
8.26 SECURITY UNLOCK
8.27 SEEK
8.28 SET FEATURES
8.28.1 Enable/disable write cache
8.28.2 Set transfer mode
8.28.3 Enable/disable automatic defect reassignment
8.28.4 Enable/disable retries
8.28.5 Vendor specific data appended
8.28.6 Set cache segments
8.28.7 Enable/disable read look-ahead
8.28.8 Enable/disable reverting to defaults
8.28.9 Enable/disable ECC
8.28.10 Set device current
8.28.11 Set maximum prefetch
8.29 SET MULTIPLE MODE
8.30 SLEEP
8.31 SMART
8.31.1 SMART DISABLE OPERATIONS
8.31.2 SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE
8.31.3 SMART ENABLE OPERATIONS
8.31.4 SMART READ ATTRIBUTE THRESHOLDS
8.31.5 SMART READ ATTRIBUTE VALUES
8.31.6 SMART RETURN STATUS
8.31.7 SMART SAVE ATTRIBUTE VALUES
8.32 STANDBY
8.33 STANDBY IMMEDIATE
8.34 WRITE BUFFER
8.35 WRITE DMA (with retries and without retries)
8.36 WRITE LONG (with retries and without retries)
8.37 WRITE MULTIPLE
8.38 WRITE SECTOR(S) (with retries and without retries)
8.39 WRITE VERIFY
9 Protocol
9.1 Power on and hardware resets
9.1.1 Power on and hardware resets - device 0
9.1.2 Power on and hardware resets - device 1
9.2 Software reset
9.2.1 Software reset - device 0
9.2.2 Software reset - device 1
9.3 PIO data in commands
9.4 PIO data out commands
9.5 Non-data commands
9.6 DMA data transfer commands
9.7 Single device configurations
9.7.1 Device 0 only configurations
9.7.2 Device 1 only configurations
10 Timing
10.1 Deskewing
10.2 Symbols
10.3 Terms
10.4 Data transfers
10.4.1 PIO data transfers
10.4.2 Multiword DMA data transfer
Annex A Connectors
A.1 40-pin connector
A.1.1 4-pin power connector
A.2 44-pin small form factor connector
A.2.1 44-pin signal assignments
A.3 68-pin small form factor connector
A.3.1 Signals
A.3.2 Signal descriptions
A.3.2.1 CD1- (Card Detect 1)
A.3.2.2 CD2- (Card Detect 2)
A.3.2.3 CS1- (Device chip select 1)
A.3.2.4 DMACK- (DMA acknowledge)
A.3.2.5 DMARQ (DMA request)
A.3.2.6 IORDY (I/O channel ready)
A.3.2.7 M/S- (Master/slave)
A.3.2.8 SELATA- (Select 68-pin ATA)
A.3.3 Removability considerations
A.3.3.1 Device recommendations
A.3.3.2 Host recommendations
Annex B Identify device data for ATA devices below 8 GB
B.1 Definitions and background information
B.2 Cylinder, head and sector addressing
B.2.1 Word 1
B.2.2 Word 3
B.2.3 Word 6
B.2.4 Use of words 53 through 58
B.2.5 Word 53
B.2.6 Word 54
B.2.7 Word 55
B.2.8 Word 56
B.2.9 Words 57-58
B.3 Orphan sectors
Annex C Signal integrity
C.1 Introduction
C.1.1 The problems
C.1.2 The goals
C.2 Termination
C.2.1 The problem
C.2.2 What are the options?
C.2.3 Design goals
C.2.4 Source termination
C.2.5 Receiver termination
C.2.6 Edge rate control
C.2.7 The solution: A combination
C.2.7.1 Example of device-end termination timing
C.2.7.2 Example of host-end termination timing calculation
C.2.8 Dual port cabling
C.3 Crosstalk
C.3.1 Coupling mechanisms
C.4 Bus timing
C.4.1 The issues
C.4.2 The influence of termination
C.4.3 Calculating rise time
C.4.4 Measuring propagation delay
C.5 Summary of guidelines
C.5.1 Guidelines for device designers
C.5.2 Guidelines for system designers
C.5.3 Guidelines for chip designers
Annex D Bibliography
Annex E ATA command set summary