AT Attachment-3 Interface (ATA-3), Revision 6

Working X3T10

Draft 2008D

Revision 6

26 October 1995

Information Technology -

AT Attachment-3 Interface

(ATA-3)

This is an internal working document of X3T10, a Technical Committee of Accredited Standards Committee X3. As such, this is not a completed standard and has not been approved. The contents may be modified by the X3T10 Technical Committee. The contents are actively being modified by X3T10. This document is made available for review and comment only.

Permission is granted to members of X3, its technical committees, and their associated task groups to reproduce this document for the purposes of X3 standardization activities without further permission, provided this notice is included. All other rights are reserved. Any commercial or for-profit replication or republication is prohibited.

ASC X3T10 Technical Editor:

Reference number

ISO/IEC ***** : 199x

ANSI X3.*** - 199x

Printed October, 25, 1995 11:16AM

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ABSTRACT

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, system integrators, software suppliers, and suppliers of intelligent storage devices.

This standard maintains a high degree of compatibility with the AT Attachment Interface with Extensions standard (ATA-2), X3.279-199x, which it replaces, and while providing additional functions, is not intended to require changes to presently installed devices or existing software.

PATENT STATEMENT

CAUTION: The developers of this standard have requested that holder's of patents that may be required for the implementation of the standard, disclose such patents to the publisher. However, neither the developers nor the publisher have undertaken a patent search in order to identify which, if any, patents may apply to this standard.

Maxtor Corporation and IBM Corporation have stated that they may have patents or pending patent applications covering subject matter in this document regarding the Security Mode Feature set. The furnishing of this document does not give you any license to those patents. You should send license inquiries, in writing, to:

Mr. Glenn H. Stevens303-678-2300

General Counsel

Maxtor Corporation

2190 Miller Drive

Longmont, Colorado 80501

Mr. John Lowe 914-742-6275

Intellectual Property and Licensing Services

IBM Corporation

500 Columbus Avenue

Thornewood, New York 10594

As of the date of publication of this standard and following calls for the identification of patents that may be required for the implementation of the standard, no other such claims have been made. No further patent search is conducted by the developer or the publisher in respect to any standard it processes. No representation is made or implied that licenses are not required to avoid infringement in the use of this standard.

DOCUMENT STATUS

Revision 0 - 28 February 1995

Revision 1 - 21 April 1995

Revision 2 - 2 June 1995

Revision 3 - 26 July 1995

Revision 4 - 6 September 1995

Per the August 22-25 working group meeting:

Revision 5 - 6 October 1995

Revision 6 - 26 October 1995

Figures

1 - ATA interface cabling diagram

2 - Cable select example

3 - Power management modes

4 - Removable modes

5 - Password set security mode power-on flow

6 - User password lost

7 - BSY and DRDY timing for diagnostic command

8 - BSY and DRDY timing for power on and hardware resets

9 - BSY and DRDY timing for software reset

10 - Example of PIO data transfer in diagram

11 - Example of PIO data transfer out diagram

12 - Example of non-data transfer diagram

13 - Example of DMA data transfer diagram

14 - PIO data transfer to/from device

15 - Multiword DMA data transfers

A.1 - 40-pin connector mounting

A.2 - Drive side connector pin numbering

A.3 - 44-pin connector

C.1 - Original IBM PC/AT architecture

C.2 - Typical PC architecture

C.3 - Typical ringing on ATA bus and its effect

C.4 - The seven basic ATA driver/receiver structures

C.5 - Schematic of SPICE simulation model

C.6 - Simulation waveforms at host and device ends of the cable

C.7 - Oscilloscope trace at device end of DIOR- signal on a typical system

C.8 - Waveforms with 22 ohms series resistor at source

C.9 - AC termination circuit at device end of cable

C.10 - Device waveform with device termination and no host termination

C.11 - Device waveform with both device and host terminations

C.12 - Signal models for device end timing calculations

C.13 - Host end signal configurations with terminations

C.14 - SPICE model for control signal out delay calculation

C.15 - Preferred connection for shared lines in dual port systems

C.16 - Crosstalk coupling mechanisms

C.17 - SPICE model of ATA cable with worst case loads

C.18 - Simulation of unterminated ATA cable with worst case loads

C.19 - Host data setup time during a read cycle

C.20 - Recommended model for I/O cell propagation delay

Tables

1 - Byte order

2 - DC characteristics

3 - AC characteristics

4 - Driver types and required pull-ups

5 - Interface signal name assignments

6 - I/O port functions and selection addresses

7 - Security mode command actions

8 - Diagnostic codes

9 - Identify device information

10 - Minor revision number

11 - Automatic standby timer periods

12 - Security password content

13 - SECURITY SET PASSWORD data content

14 - Identifier and security level bit interaction

15 - SET FEATURES register definitions

16 - Transfer/mode values

17 - Device attribute thresholds data structure

18 - Individual threshold data structure

19 - Device attributes data structure

20 - Individual attribute data structure

21 - PIO data transfer to/from device

22 - Multiword DMA data transfer

A.1 - 40-pin connector interface signals

A.2 - DC interface using 4-pin power connector

A.3 - Signal assignments for 44-pin ATA

A.4 - Signal assignments for 68-pin ATA

B.1 - Word 1 value

C.1 - Recommanded termination

C.2 - Typical device end propagation delay times

C.3 - Typical host end propagation delay times

C.4 - Possible sharing of ATA signals in dual port configurations

E.1 - Command matrix

E.2 - Commands sorted by command value

E.3 - Command codes and parameters

E.4 - Status and error usage

1. Foreword

(This foreward is not part of American National Standard X3.***-199*.)

This standard encompasses the following:

Clause 1 describes the scope.

Clause 2 lists the normative references.

Clause 3 provides definitions, abbreviations, and conventions used within this document.

Clause 4 contains the electrical and mechanical characteristics; covering the interface cabling requirements of the interface and DC cables and connectors.

Clause 5 contains the signal descriptions of the AT Attachment Interface.

Clause 6 contains descriptions of the registers of the AT Attachment Interface.

Clause 7 describes the general operating requirements of the AT Attachment Interface.

Clause 8 contains descriptions of the commands of the AT Attachment Interface.

Clause 9 contains an overview of the protocol of the AT Attachment Interface.

Clause 10 contains the interface timing diagrams.

Annex A is normative.

Annexes B through E are informative.

 

 

 

 

2. Introduction

The first IBM PCä (Personal Computer) introduced had no hard disk storage capability. When the IBM PC ATä was developed, a hard disk was the key to system performance, and processor to hard disk interface became a de facto industry interface for the inclusion of hard disks in personal computers.

In October 1988, a number of device suppliers formed the Common Access Method Committee to encourage an industry-wide effort to adopt a common software interface to dispatch input/output requests to SCSI devices. Although this was the primary objective, a secondary goal was to specify what was known as the AT Attachment interface. This resulted in the development of the AT Attachment Interface For Disk Drives standard.

As personal computer type systems continued to evolved, there was a need to extend the capabilities of the interface. The lap-top and small computer systems needed to modify the mechanical aspects of the interface. High performance systems needed to have enhanced transfer rates. This evolutionary process has led to today’s AT Attachment-3 Interface.

 

1. Scope

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, system integrators, software suppliers, and suppliers of intelligent storage devices.

The application environment for the AT Attachment Interface is any host system that has storage devices contained within the processor enclosure.

This standard defines the connectors and cables for physical interconnection between host and storage device, as well as, the electrical and logical characteristics of the interconnecting signals. It also defines the operational registers within the storage device, and the commands and protocols for the operation of the storage device.

This standard maintains a high degree of compatibility with the AT Attachment Interface with Extensions (ATA-2) standard, X3.279-199x, which it replaces, and while providing additional functions, is not intended to require changes to presently installed devices or existing software.

 

2. Normative references

None.

 

 

3. Definitions, abbreviations, and conventions

1. Definitions and abbreviations

For the purposes of this American National Standard, the following definitions apply.

3.1.1 ATA (AT Attachment) : ATA defines the physical, electrical, transport, and command protocols for the internal attachment of block storage devices.

3.1.2 ATA-1 device : A device which complies with ANSI X3.221-1994, the AT Attachment Interface for Disk Drives.

3.1.3 ATA-2 device : A device which complies with ANSI X3.279-199x, the AT Attachment Interface with Extensions.

3.1.4 AWG : American Wire Gauge.

3.1.5 Command acceptance : A command is considered accepted whenever the host writes to the Command Register and the device currently selected has its BSY bit equal to zero. An exception exists for the EXECUTE DIAGNOSTIC command (see 8.5).

3.1.6 CHS (Cylinder-head-sector) : This term defines the addressing of the device as being by cylinder number, head number and sector number.

3.1.7 Data block : This term describes a unit of data words transferred using PIO data transfer. A data block is transferred between the host and the device as a complete unit. A data block is a sector, except for data blocks of a READ MULTIPLE, WRITE MULTIPLE, READ LONG and WRITE LONG commands. In the cases of READ MULTIPLE and WRITE MULTIPLE commands, the size of the data block may be changed in multiples of sectors by the SET MULTIPLE MODE command. In the cases of READ LONG and WRITE LONG, the size of the data block is a sector plus a vendor specific number of bytes. The default length of the vendor specific bytes associate with the READ LONG and WRITE LONG commands is four bytes, but may be changed by use of the SET FEATURES command.

3.1.8 Device : Device is a storage peripheral. Traditionally, a device on the ATA interface has been a hard disk drive, but any form of storage device may be placed on the ATA interface provided it adheres to this standard.

3.1.9 Device selection : A device is selected when the DEV bit of the Drive/Head register is equal to the device number assigned to the device by means of a Device 0/Device 1 jumper or switch, or use of the CSEL signal.

3.1.10 DMA (Direct memory access) : A means of data transfer between device and host memory without processor intervention.

3.1.11 LBA (Logical block address) : This term defines the addressing of the device as being by the linear mapping of sectors.

3.1.12 Master : In ATA-1, Device 0 has also been referred to as the master. Throughout this document the term Device 0 is used.

3.1.13 Optional : This term describes features which are not required by thise standard. However, if any optional feature defined by the standard is implemented, it shall be done in the way defined by the standard. Describing a feature as optional in the text is done to assist the reader.

3.1.14 PIO (Programmed input/output) : A means of accessing device registers. PIO is also used to describe one form of data transfers. PIO data transfers are performed by the host processor utilizing PIO register accesses to the Data register.

3.1.15 Reserved : Reserved bits, bytes, words, fields and code values are set aside for future standardization. Their use and interpretation may be specified by future extensions to this or other standards. A reserved bit, byte, word or field shall be set to zero, or in accordance with a future extension to this standard. The recipient shall not check reserved bits, bytes, words or fields. Receipt of reserved code values in defined fields shall be treated as an error.

3.1.16 Sector : A uniquely addressable set of 256 words (512 bytes).

3.1.17 Slave : In ATA-1, Device 1 has also been referred to as the slave. Throughout this document the term Device 1 is used.

3.1.18 S.M.A.R.T. : Self-mMonitoring, aAnalysis, and rReporting tTechnology for prediction of device degradation and/or faults. Throughout this document this is noted as SMART.

3.1.19 Unrecoverable error : An unrecoverable error is defined as having occurred at any point when the device sets either the ERR bit or the DF bit to one and the BSY bit to zero in the Status register when processing a command.

3.1.20 VS (Vendor specific) : This term is used to describe bits, bytes, fields and code values which are reserved for vendor specific purposes. These bits, bytes, fields and code values are not described in this standard, and may vary among vendors. This term is also applied to levels of functionality whose definition is left to the vendor.

Note 1: Industry practice could result in conversion of a Vendor Specific bit, byte, field or code value into a defined standard value in a future standard.

2. Conventions

If there is a conflict between text, figures and tables, the precedence shall be tables, figures, then text.

1. Keywords

Several keywords are used to differentiate between different levels of requirements and optionality, as follows:

expected - A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard. Other hardware and software design models may also be implemented.

may - A keyword that indicates flexibility of choice with no implied preference.

shall - A keyword indicating a mandatory requirement. Designers are required to implement all such mandatory requirements to ensure interoperability with other standard conformant products.

should - A keyword indicating flexibility of choice with a strongly preferred alternative. Equivalent to the phrase "it is recommended".

obsolete - A keyword indicating items that were defined in ATA-1 or ATA-2 but have been removed from this standard.

mandatory - A keyword indicating items to be implemented as defined by this standard.

Lower case is used for words having the normal English meaning. Certain words and terms used in this American National Standard have a specific meaning beyond the normal English meaning. These words and terms are defined either in Clause 3 or in the text where they first appear.

The names of abbreviations, commands, fields, and acronyms used as signal names are in all uppercase (e.g., IDENTIFY DEVICE). Fields containing only one bit are usually referred to as the "name" bit instead of the "name" field. (See 3.2.4 for the naming convention used for naming bits.)

Names of device registers begin with a capital letter (e.g., Cylinder Low register).

2. Numbering

Numbers that are not immediately followed by a lower-case "b" or "h" are decimal values. Numbers that are immediately followed by a lower-case "b" (e.g., 01b) are binary values. Numbers that are immediately followed by a lower-case "h" (e.g., 3Ah) are hexadecimal values.

3. Signal conventions

Signal names are shown in all upper case letters.

All signals are either high active or low active signals. A dash character (-) at the end of a signal name indicates it is a low active signal. A low active signal is true when it is below V_iL, and is false when it is above V_iH. No dash at the end of a signal name indicates it is a high active signal. A high active signal is true when it is above V_iH, and is false when it is below V_iL.

Asserted means that the signal is driven by an active circuit to its true state. Negated means that the signal is driven by an active circuit to its false state. Released means that the signal is not actively driven to any state. Some signals have bias circuitry that pull the signal to either a true state or false state when no signal driver is actively asserting or negating the signal. These cases are noted under the description of the signal, and their released state is stated.

Control signals that may be used for two mutually exclusive functions are identified with their two names separated by a colon.

4. Bit conventions

Bit names are shown in all upper case letters except where a lower case n precedes a bit name. If there is no preceding n, then when BIT is equalset to one the meaning of the bit is true, and when BIT is equalcleared to zero the meaning of the bit is false. If there is a preceding n, then when nBIT is equalcleared to zero the meaning of the bit is true and when nBIT is equalset to one the meaning of the bit is false.

5. Byte ordering for data transfers

Assuming a block of data contains "n" bytes of information, and the bytes are labeled Byte(0) through Byte(n-1), where Byte(0) is first byte of the block, and Byte(n-1) is the last byte of the block. When such a block of data is transferred on the interface, the bytes shall be presented as shown in Table 1.

Table 1 - Byte order

DD 15

DD 14

DD 13

DD 12

DD 11

DD 10

DD 9

DD 8

DD 7

DD 6

DD 5

DD 4

DD 3

DD 2

DD 1

DD 0

First transfer

Byte (1)

Byte (0)

Second transfer

Byte (3)

Byte (2)

........

Last transfer

Byte (n-1)

Byte (n-2)

Note 2: The above description is for data on the ATA Interface. Host systems and/or host adapters may cause the order of data, as seen in the memory of the host, to be different.