AT Attachment-3 Interface (ATA-3), Revision 6

1-3 Forward, Introduction, Scope, Normative references, Definitions, abbreviations, and conventions
4 Interface physical and electrical requirements
5 Interface signal assignments and descriptions
6 Interface register definitions and descriptions
7 General operational requirements
8 Command descriptions
9 Protocol
10 Timing
Annex A Connectors
Annex B Identify device data for ATA devices below 8 GB
Annex C Signal integrity
Annex D Bibliography
Annex E ATA command set summary

  • Protocol

    • Commands can be grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below.

    For all commands, the host first checks if the BSY bit is equal to one, and should proceed no further unless and until the BSY bit is equal to zero. For most commands, the host shall also wait for the DRDY bit to be equal to one before proceeding. The commands shown with DRDY=x can be executed when the DRDY bit is equal to zero.

    Data transfers may be accomplished in more ways than are described below, but these sequences should work with all known implementations of ATA devices.

    A device shall maintain either the BSY bit equal to one or the DRQ bit equal to one at all times until the command is completed. The INTRQ signal is used by the device to signal most, but not all, times when the BSY bit is changed from one to zero during command execution.

    A command shall only be interrupted with a hardware or software reset. The result of writing to the Command register while the BSY bit is equal to one or the DRQ bit is equal to one is unpredictable and may result in data corruption.

    1. Power on and hardware resets

      2. This clause describes the algorithm and timing relationships for Devices 0 and 1 during the processing of power on and hardware resets.

      The timing assumes the following:

      a) DASP- is asserted by Device 1 and received by Device 0 at power-on or hardware reset to indicate the presence of Device 1. At all other times it is asserted by Device 0 or Device 1 to indicate when a device is active;

      b) PDIAG- is asserted by Device 1 and detected by Device 0. It is used by Device 1 to indicate to Device 0 that it has completed diagnostics without error and is ready to accept commands from the Host (BSY bit is cleared). This does not indicate that the device is ready, only that it can accept commands.

      1. Power on and hardware resets - device 0

        2. a) Host asserts RESET- for a minimum of 25 m s;

        b) Device 0 sets the BSY bit no later than 400 ns after RESET- is negated;

        c) Device 0 negates DASP- no later than 1 ms after RESET- is negated;

        d) Device 0 samples for at least 450 ms for DASP- to be asserted from Device 1. This sampling starts 1 ms after RESET- is negated;

        e) Device 0 performs hardware initialization and diagnostics;

        f) Device 0 may revert to its default condition;

        g) If Device 0 detected that DASP- was asserted during step d), then Device 0 waits up to 31 s for Device 1 to assert PDIAG-. Sampling of PDIAG- starts 1 ms after RESET is negated. If PDIAG- is asserted within 31 s, Device 0 clears bit 7 equal to zero in the Error Register, else Device 0 sets bit 7 equal to one in the Error Register. If DASP- assertion was not detected in step d) Device 0 clears bit 7 equal to zero in the Error Register. In either case the device shall set the Sector Count register to 01h, the Sector Number register to 01h, the Cylinder Low register to 00h, the Cylinder High register to 00h, and the Device/Head register to 00h. Device 0 shall store whether or not Device 1 was detected in step d) because this information is need in order to process any Software reset or EXECUTE DEVICE DIAGNOSTIC command later;

        h) Device 0 posts diagnostic results to bits 6-0 of the Error Register;

        i) Device 0 clears the BSY bit when ready to accept commands that do not require the DRDY bit to be equal to 1. Device 0 shall clear the BSY bit no later than 31 s from the time that RESET- is negated;

        j) Device 0 sets the DRDY bit when ready to accept any command.


        NOTE 23: Steps i) and j) may occur at the same time. While no maximum time is specified for the DRDY bit to be set to one, a host should allow up to 30 s for the DRDY bit to become 1. See Figure 8.

      2. Power on and hardware resets - device 1

      a) Host asserts RESET- for a minimum of 25 m s;

      b) Device 1 sets the BSY bit no later than 400 ns after RESET- is negated;

      c) Device 1 negates DASP- no later than 1 ms after RESET- is negated;

      d) Device 1 negates PDIAG- before asserting DASP-;

      e) Device 1 asserts DASP- no later than 400 ms after RESET- is negated;

      f) Device 1 performs hardware initialization and diagnostics;

      g) Device 1 may revert to its default condition;

      h) Device 1 posts diagnostic results to the Error Register.

      i) Device 1 clears the BSY bit when ready to accept commands that do not require the DRDY bit to be equal to 1;

      j) If Device 1 passed its diagnostics without error in step f), Device 1 asserts PDIAG-. If the diagnostics failed, Device 1 does not assert PDIAG- and continues to the next step. Device 1 shall clear the BSY bit, and optionally assert PDIAG-, no later than 30 s from the time RESET- is negated. The device shall set the Sector Count register to 01h, the Sector Number register to 01h, the Cylinder Low register to 00h, the Cylinder High register to 00h, and the Device/Head register to 00h;

      k) Device 1 sets the DRDY bit when ready to accept any command;

      NOTE 24: Steps i), j) and k) may occur at the same time. While no maximum time is specified for the DRDY bit to be set to one, a host should allow up to 30 s for the DRDY bit to become 1. See Figure 8.

      l) Device 1 negates DASP- after the first command is received or negates DASP- if no command is received within 31 s after RESET- is asserted.

      Figure 8 - BSY and DRDY timing for power on and hardware resets

    2. Software reset

      3. This clause describes the algorithm and timing relationships for Devices 0 and 1 during the processing of software resets.

      Note 25: Some devices may require SRST be set for a minimum of 5 m s.

      1. Software reset - device 0

        2. a) Host sets the SRST bit to one in the Device Control register;

        b) Device 0 sets BSY bit no later than 400 ns after detecting that the SRST bit is equal to one;

        c) Device 0 performs hardware initialization and diagnostics;

        d) Device 0 may revert to its default condition;

        e) Device 0 posts diagnostic results to the Error Register;

        f) Device 0 waits for the host to clear the SRST bit to zero;

        g) If Device 0 detected that Device 1 is present during the most recent power on or hardware reset sequence, then Device 0 waits up to 31 s from the time that the SRST bit to become zero for Device 1 to assert PDIAG-. Sampling of PDIAG- starts 1ms after SRST is cleared to zero. If PDIAG- is asserted within 31 s, Device 0 clears bit 7 equal to zero in the Error Register, else Device 0 sets bit 7 equal to one in the Error Register. If device 1 was not detected during the most recent power up or hardware reset sequence, then Device 0 clears bit 7 equal to zero in the Error register. In either case the device shall set the Sector Count register to 01h, the Sector Number register to 01h, the Cylinder Low register to 00h, the Cylinder High register to 00h, and the Device/Head register to 00h;

        h) Device 0 clears the BSY bit when ready to accept commands that do not require the DRDY bit to be equal to 1. Device 0 shall clear the BSY bit no later than 31 s from the time that the host clears the SRST bit equal to zero;

        Note 26: Steps g) and h) may occur very rapidly.

        i) Device 0 sets the DRDY bit when ready to accept any command.

        NOTE 27: Steps h) and i) may occur at the same time. While no maximum time is specified for the DRDY bit to become equal to 1 to occur, a host should allow up to 30 s for the DRDY bit to be set to one. See Figure 9.

      2. Software reset - device 1

      a) Host sets SRST bit to one in the Device Control register;

      b) Device 1 set the BSY bit no later than 400 ns after detecting that the SRST bit to equal to one;

      c) Device 1 negates PDIAG- no later than 1 ms after detecting that the SRST bit is one;

      d) Device 1 perform hardware initialization and diagnostics;

      e) Device 1 may revert to its default condition;

      f) Device 1 posts diagnostic results to the Error Register;

      g) Device 1 waits for the host to clear the SRST bit equal to zero;

      h) Device 1 clears the BSY bit when ready to accept commands that do not require the DRDY bit to be equal to 1;

      i) If Device 1 passed its diagnostics without error in step d), Device 1 asserts PDIAG-. If the diagnostics failed, Device 1 does not assert PDIAG- and continues to the next step. Device 1 shall clear the BSY bit, optionally assert PDIAG-, no later than 30 s from the time the host clears the SRST bit to zero. The device shall set the Sector Count register to 01h, the Sector Number register to 01h, the Cylinder Low register to 00h, the Cylinder High register to 00h, and the Device/Head register to 00h;

      j) Device 1 sets the DRDY bit when ready to accept any command.

      NOTE 28: Steps h), i) and j) may occur at the same time. While no maximum time is specified for the DRDY bit to be set to one, a host should allow up to 30 s for the DRDY bit to become one. See Figure 9.

       

      Figure 9 - BSY and DRDY timing for software reset

    3. PIO data in commands

    This class includes:

    Execution of this class of command includes the transfer of one or more blocks of data from the device to the host. The following steps describe the processing of a PIO data in command. This description does not include all possible error conditions. See Figure 10.

    Figure 10 - Example of PIO data transfer in diagram (continued)

    Figure 10 - Example of PIO data transfer in diagram (concluded)

     

        1. PIO data out commands

    This class includes:

    Execution of this class of command includes the transfer of one or more blocks of data from the host to the device. The following steps describe the processing of a PIO data out command. This description does not include all possible error conditions. See Figure 11.

     

    Figure 11 - Example of PIO data transfer out diagram (continued)

    Figure 11 - Example of PIO data transfer out diagram (concluded)

     

        1. Non-data commands

    This class includes:

    Execution of these commands involves no data transfer. The following steps describe the processing of a no data transfer command. This description does not include all possible error conditions.

    See the EXECUTE DEVICE DIAGNOSTICS command description in 8.5, the NOP command description in 8.13 and the SLEEP command description in 8.30 for additional protocol requirements. See Figure 12.

    Figure 12 - Example of Nnon-data transfer diagram

     

        1. DMA data transfer commands

    This class comprises:

    Data transfers using DMA commands differ in two ways from PIO transfers:

    1. data transfers are performed using the DMA channel;

    2. A Single interrupt is issued at the completion of the command.

    Initiation of the DMA transfer commands is identical to the READ SECTOR(S) or WRITE SECTOR(S) commands except that the host initializes the DMA channel prior to issuing the command.

    The interrupt handler for DMA transfers is different in that no intermediate sector interrupts are issued on multi-sector commands.

    The following steps describe the execution of a DMA command. See Figure 13.

    Figure 13 - Example of DMA data transfer diagram (continued)

    Figure 13 - Example of DMA data transfer diagram (concluded)

     

        1. Single device configurations

          1. Device 0 only configurations

    In a single device configuration where Device 0 is the only device and the host selects Device 1, Device 0 may respond to accesses of the Command Block and Control Block registers in one of two methods. These two methods exist because previous versions of the ATA standard did not specify the required behavior for this configuration. The first method is the recommended implementation.

    The first method is:

      1. A write to the Device Control register shall complete as if Device 0 was the selected device;

      2. A write to a Command Block register, other than the Command register, shall complete as if Device 0 was selected;

      3. A write to the Command register is ignored;

      4. A read of the Control Block or Command Block registers, other than the Status or Alternate Status registers, shall complete as if Device 0 was selected;

      5. A read of the Status or Alternate status register returns the value 00h;

    Note 29: IDX is vendor specific and might change following reset or power mode changes resulting in values for status other than 00h.

    The second method requires that Device 0 implement an Error, Status and Alternate Status register that is used whenever Device 1 is selected.

    The second method is:

    a) The Device 1 Error, Status and Alternate status registers are set to 00h by a reset;

    Note 30: IDX is vendor specific and might change following reset or power mode changes resulting in values for status other than 00h;

    1. A write to the Device Control register shall complete as if Device 0 was the selected device;

    2. A write to a Command Block register, other than the Command register, shall complete as if Device 0 was selected;

    3. A write to the Command register with a command code other than the INITIALIZE DEVICE PARAMETERS or EXECUTE DEVICE DIAGNOSTICS command causes the Device 1 Error, Status, and Alternate Status registers to be used as follows:

    1. the BSY bit is set in the Device 1 Status register;

    2. the ABRT bit is set in the Device 1 Error register;

    3. the ERR bit is set in the Device 1 Status register;

    4. the BSY bit is cleared in the Device 1 Status register;

    5. if the nIEN bit in the Device Control Register is cleared, the INTRQ signal is asserted.

    e) An EXECUTE DEVICE DIAGNOSTIC command is executed as if it addressed to Device 0;

    f) An INITIALIZE DEVICE PARAMETERS command is executed as if Device 1 is present and is

    actually executing the command. The command shall have no effect of the device parameters

    of Device 0;

    g) A read of the Control Block or Command Block registers, other than the Status or Alternate

    Status registers, shall complete as if Device 0 was selected;

    h) A read of the Error, Status or Alternate status register returns the value in the device 1 copy of

    these registers. The Device 1 status registers shall contain 00h following a reset and the value

    01h following an attempt to execute a command, other than EXECUTE DEVICE DIAGNOSTICS

    or INITIALIZE DEVICE PARAMETERS, on Device 1.

     

          1. Device 1 only configurations

    Host support of Device 1 only configurations is host specific.

    In a single device configuration where Device 1 is the only device and the host selects Device 0, Device 1 shall respond to accesses of the Command Block and Control Block registers in the same way it would if Device 0 was present. This is because Device 1 cannot determine if Device 0 is, or is not, present.

    Host implementation of read and write operations to the Command and Control Block registers of non-existent Device 0 are host specific.

    Note 31: The remainder of this section is a host implementation note.

    The host implementor should be aware of the following when supporting Device 1 only configurations:

    1) Following a hardware reset or software reset, Device 1 will not be selected. The following steps may be used to reselect Device 1:

    a) Write to the Device/Head register with DRV bit set to one;

    b) Using one or more of the Command Block registers that can be both written and read, such as the Sector Count or Sector Number, write a data pattern other than 00h or FFh to the register(s);

    c) Read the register(s) written in step b). If the data read is the same as the data written, proceed to step e);

    d) Repeat steps a) to c) until the data matches in step c) or until 31 s has past. After 31 s it can probably be assumed that Device 1 is not functioning properly;

    e) Read the Status register and Error registers. Check the Status and Error register contents for any error conditions that Device 1 may have posted.

    2) Following the execution of an EXECUTE DEVICE DIAGNOSTICS command, Device 1 will not be selected. Also, no interrupt will be generated to signal the completion of the command. After writing the EXECUTE DEVICE DIAGNOSTIC command to the Command register, execute steps a) to e) as described in 1) above;

    3) At all other times, do not write zero into the DRV bit of the Device/Head register. All other commands execute normally.