ATA-3, Rev 6

AT Attachment-3 Interface (ATA-3), Revision 6

1-3 Forward, Introduction, Scope, Normative references, Definitions, abbreviations, and conventions
4 Interface physical and electrical requirements
5 Interface signal assignments and descriptions
6 Interface register definitions and descriptions
7 General operational requirements
8 Command descriptions
9 Protocol
10 Timing
Annex A Connectors
Annex B Identify device data for ATA devices below 8 GB
Annex C Signal integrity
Annex D Bibliography
Annex E ATA command set summary

Timing

Deskewing

The host shall provide cable deskewing for all signals originating from the controller. The device shall provide cable deskewing for all signals originating at the host.

All timing values and diagrams are shown and measured at the connector of either device connected to the ATA interface. No values are given for measurement at the host interface.

Symbols

Certain symbols are used in the timing diagrams. These symbols and their respective definitions are listed below.

* All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition.

Terms

The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics.

In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted e.g., the following illustrates the representation of a signal named TEST going from negated to asserted and back to negated, based on the polarity of the signal.

Data transfers

The minimum cycle time supported by the device in PIO Mode 3, 4 and Multiword DMA Mode 1, 2 respectively shall always be greater than or equal to the minimum cycle time defined by the associated Mode e.g. a drive supporting PIO Mode 4 timing shall not report a value less than 120 ns, the minimum cycle time defined for Mode 4 PIO Timings.

PIO data transfers

Figure 14 defines the relationships between the interface signals for PIO data transfers. Peripherals reporting support for PIO Transfer Mode 3 or 4 shall power up in a PIO Transfer Mode 0, 1 or 2.

For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the Identify Drive parameter list. The value in word 68 shall not be less than the value shown in Table 21.

IORDY shall be supported when PIO Mode 3 or 4 are the current mode of operation.

Figure 14 - PIO data transfer to/from device

Table 21 PIO data transfer to/from device

PIO timing parameters

Mode 0
ns

Mode 1
ns

Mode 2
ns

Mode 3
ns

Mode 4
ns

Note

t0

Cycle time

(min)

600

383

240

180

120

1

t1

Address valid to DIOR-/DIOW- setup

(min)

70

50

30

30

25

t2

DIOR-/DIOW- 16-bit

(min)

165

125

100

80

70

1

t2i

DIOR-/DIOW- recovery time

(min)

-

-

-

70

25

1

t3

DIOW- data setup

(min)

60

45

30

30

20

t4

DIOW- data hold

(min)

30

20

15

10

10

t5

DIOR- data setup

(min)

50

35

20

20

20

t6

DIOR- data hold

(min)

5

5

5

5

5

t6Z

DIOR- data tristate

(max)

30

30

30

30

30

2

t9

DIOR-/DIOW- to address valid hold

(min)

20

15

10

10

10

tRd

Read Data Valid to IORDY active
(if IORDY initially low after tA)

(min)

0

0

0

0

0

tA

IORDY Setup time

35

35

35

35

35

3

tB

IORDY Pulse Width

(max)

1250

1250

1250

1250

1250

Notes:
1 t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirements is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the devices identify drive data. A device implementation shall support any legal host implementation.
2 This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is no longer driven by the device (tri-state).
3 The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device is not driving IORDY negated at the tA after the activation of DIOR- or DIOW-, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIOR- or DIOW-, then tRD shall be met and t5 is not applicable.

Multiword DMA data transfer

The timings associated with Multiword DMA Transfers are defined in Figure 15.

For Multiword DMA modes 1 and above, the minimum value of t0 is specified by word 65 in the Identify Drive parameter list. The value in word 65 shall not be less than the value shown in Table 22.

Devices reporting support for Multiword DMA Transfer Mode 2 shall also support Multiword DMA Transfer Mode 0 and 1 and shall power up with Mode 0 as the default Multiword DMA Mode.

Figure 15 - Multiword DMA data transfer

Table 22 - Multiword DMA data transfer

Multiword DMA timing parameters

Mode 0
ns

Mode 1
ns

Mode 2
ns

Note

t0

Cycle time

(min)

480

150

120

1

tC

DMACK to DMARQ delay

tD

DIOR-/DIOW-

(min)

215

80

70

1

tE

DIOR- data access

(max)

150

60

tF

DIOR- data hold

(min)

5

5

5

tG

DIOWR-/DIOW- data setup

(min)

100

30

20

tH

DIOW- data hold

(min)

20

15

10

tI

DMACK to DIOR-/DIOW- setup

(min)

0

0

0

tJ

DIOR-/DIOW- to DMACK hold

(min)

20

5

5

tKr

DIOR- negated pulse width

(min)

50

50

25

1

tKw

DIOW- negated pulse width

(min)

215

50

25

1

tLr

DIOR- to DMARQ delay

(max)

120

40

35

tLw

DIOW- to DMARQ delay

(max)

40

40

35

tZ

DMACK- to tristate

(max)

20

25

25

Notes:
1 t0 is the minimum total cycle time, tD is the minimum command active time, and tK (tKr or tKw, as appropriate) is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, tD, tK shall be met. The minimum total cycle time requirement, t0, is greater than the sum of tD and tK. This means a host implementation can lengthen either or both tD or tK to ensure that t0 is equal to the value reported in the devices identify drive data.. A device implementation shall support any legal host implementation.

	PIO timing parameters		Mode 0 ns	Mode 1 ns	Mode 2 ns	Mode 3 ns	Mode 4 ns	Note
t0	Cycle time	(min)	600	383	240	180	120	1
t1	Address valid to DIOR-/DIOW- setup	(min)	70	50	30	30	25
t2	DIOR-/DIOW- 16-bit	(min)	165	125	100	80	70	1
t2i	DIOR-/DIOW- recovery time	(min)	-	-	-	70	25	1
t3	DIOW- data setup	(min)	60	45	30	30	20
t4	DIOW- data hold	(min)	30	20	15	10	10
t5	DIOR- data setup	(min)	50	35	20	20	20
t6	DIOR- data hold	(min)	5	5	5	5	5
t6Z	DIOR- data tristate	(max)	30	30	30	30	30	2
t9	DIOR-/DIOW- to address valid hold	(min)	20	15	10	10	10
tRd	Read Data Valid to IORDY active (if IORDY initially low after tA)	(min)	0	0	0	0	0
tA	IORDY Setup time		35	35	35	35	35	3
tB	IORDY Pulse Width	(max)	1250	1250	1250	1250	1250
Notes: 1 t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirements is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the devices identify drive data. A device implementation shall support any legal host implementation. 2 This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is no longer driven by the device (tri-state). 3 The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device is not driving IORDY negated at the tA after the activation of DIOR- or DIOW-, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIOR- or DIOW-, then tRD shall be met and t5 is not applicable.

	Multiword DMA timing parameters		Mode 0 ns	Mode 1 ns	Mode 2 ns	Note
t0	Cycle time	(min)	480	150	120	1
tC	DMACK to DMARQ delay
tD	DIOR-/DIOW-	(min)	215	80	70	1
tE	DIOR- data access	(max)	150	60
tF	DIOR- data hold	(min)	5	5	5
tG	DIOWR-/DIOW- data setup	(min)	100	30	20
tH	DIOW- data hold	(min)	20	15	10
tI	DMACK to DIOR-/DIOW- setup	(min)	0	0	0
tJ	DIOR-/DIOW- to DMACK hold	(min)	20	5	5
tKr	DIOR- negated pulse width	(min)	50	50	25	1
tKw	DIOW- negated pulse width	(min)	215	50	25	1
tLr	DIOR- to DMARQ delay	(max)	120	40	35
tLw	DIOW- to DMARQ delay	(max)	40	40	35
tZ	DMACK- to tristate	(max)	20	25	25
Notes: 1 t0 is the minimum total cycle time, tD is the minimum command active time, and tK (tKr or tKw, as appropriate) is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, tD, tK shall be met. The minimum total cycle time requirement, t0, is greater than the sum of tD and tK. This means a host implementation can lengthen either or both tD or tK to ensure that t0 is equal to the value reported in the devices identify drive data.. A device implementation shall support any legal host implementation.