ATA-3, Rev 6

AT Attachment-3 Interface (ATA-3), Revision 6

1-3 Forward, Introduction, Scope, Normative references, Definitions, abbreviations, and conventions
4 Interface physical and electrical requirements
5 Interface signal assignments and descriptions
6 Interface register definitions and descriptions
7 General operational requirements
8 Command descriptions
9 Protocol
10 Timing
Annex A Connectors
Annex B Identify device data for ATA devices below 8 GB
Annex C Signal integrity
Annex D Bibliography
Annex E ATA command set summary

Interface register definitions and descriptions

Device addressing considerations

In traditional controller operation, only the selected device receives commands from the host following selection. In this standard, the register contents go to both devices (and their embedded controllers). The host discriminates between the two by using the DEV bit in the Device/Head register.

Data is transferred in parallel either to or from host memory to the device's buffer under the direction of commands previously transferred from the host. The device performs all of the operations necessary to properly write data to, or read data from, the media. Data read from the media is stored in the device's buffer pending transfer to the host memory and data is transferred from the host memory to the device's buffer to be written to the media.

The devices using this interface shall be programmed by the host computer to perform commands and return status to the host at command completion. When two devices are daisy chained on the interface, commands are written in parallel to both devices, and for all except the EXECUTE DEVICE DIAGNOSTICS command, only the selected device executes the command. On an EXECUTE DEVICE DIAGNOSTICS command addressed to Device 0, both devices shall execute the command, and Device 1 shall post its status to Device 0 via PDIAG-.

Devices are selected by the DEV bit in the Device/Head register (see 6.2.8). When the DEV bit is equal to zero, Device 0 is selected. When the DEV bit is equal to one, Device 1 is selected. When devices are daisy chained, one shall be set as Device 0 and the other as Device 1.

I/O register descriptions

Communication to or from the device is through an I/O Register that routes the input or output data to or from registers addressed by the signals from the host (CS0-, CS1-, DA (2:0), DIOR- and DIOW-).

The Command Block Registers are used for sending commands to the device or posting status from the device. The Control Block Registers are used for device control and to post alternate status.

Anytime a command is in progress, that is, from the time the Command register is written until the device has completed the command and posted ending status, the device shall have either BSY or DRQ set to one. If the Command Block registers are read by the host when BSY or DRQ is set to one, the content of all register bits and fields except BSY and DRQ in the Status and Alternate Status registers is indeterminant. If the host writes to any Command Block register when BSY or DRQ is set to one, the results are indeterminant and may result in the command in progress ending with a command abort error.

ForWhen performing DMA transfers, BSY and DRQ shall both be cleared to zero within 400ns of INTRQ assertion. This signals the completion of a DMA command.

ForWhen performing PIO transfers, BSY and DRQ shall both be cleared to zero within 400ns of the transfer of the final byte of data. This assertion signals the completion of a PIO data transfer command.

Table 6 lists these registers and the addresses that select them.

Table 6 - I/O port functions and selection addresses

Addresses

Functions

CS0-

CS1-

DA2

DA1

DA0

Read (DIOR-)

Write (DIOW-)

N

N

x

x

x

Data bus high impedence

Not used

Control block registers

N

A

0

x

x

Data bus high impedence

Not used

N

A

1

0

x

Data bus high impedence

Not used

N

A

1

1

0

Alternate Status

Device Control

N

A

1

1

1

(See note 1)

Not used

Command block registers

A

N

0

0

0

Data

Data

A

N

0

0

1

Error

Features

A

N

0

1

0

Sector Count

Sector Count

A

N

0

1

1

Sector Number
LBA (7:0) (See note 2)

Sector Number
LBA (7:0) (See note 2)

A

N

1

0

0

Cylinder Low
LBA (15:8) (See note 2)

Cylinder Low
LBA (15:8) (See note 2)

A

N

1

0

1

Cylinder High
LBA (23:16) (See note 2)

Cylinder High
LBA (23:16) (See note 2)

A

N

1

1

0

Device/Head
LBA (27:24) (See note 2)

Device/Head
LBA (27:24)(See note 2)

A

N

1

1

1

Status

Command

A

A

x

x

x

Invalid address

Invalid address

Key:
A = signal asserted, N = signal negated, x = don’t care
Notes:
1 This register is obsolete. It is recommended that a device not respond to a read of this address. If a device does respond, it shall not drive the DD7 signal to prevent possible conflict with floppy disk implementations.
2 Mapping of registers in LBA translation.

Each register description in the following clauses contain the following format:

ADDRESS - the CS and DA address of the register.

DIRECTION - indicates if the register is read/write, read only, or write only from the host.

ACCESS RESTRICTIONS - indicates when the register may be accessed.

EFFECT - indicates the effect of accessing the register.

FUNCTIONAL DESCRIPTION - describes the function of the register.

FIELD/BIT DESCRIPTION - describes the content of the register.

Alternate Status register

ADDRESS - CS(1:0)=1h, DA(2:1)=6h

DIRECTION - This register is read only. If this address is written to by the host, the Device Control register is written. The contents of the this register and all other Command Block registers are not valid while a device is in the Sleep mode.

ACCESS RESTRICTIONS - When the BSY bit is equal to zero, the other bits in this register shall be valid.

EFFECT - Reading this register shall not perform an interrupt acknowledge or clear a pending interrupt.

FUNCTIONAL DESCRIPTION - This register contains the same information as the Status register in the command block.

FIELD/BIT DESCRIPTION -

7	6	5	4	3	2	1	0
BSY	DRDY	DF	DSC	DRQ	CORR	IDX	ERR

See 6.2.13 for definitions of the bits in this register.

Command register

ADDRESS - CS(1:0)=2h, DA(2:1)=7h

DIRECTION - This register is write-only. If this address is read by the host, the Status register is read.

ACCESS RESTRICTIONS - This register shall only be written when BSY and DRQ are both equal to zero and DMARQ is not asserted. The contents of the this register and all other Command Block registers are not valid while a device is in the Sleep mode.

EFFECT - Command processing begins when this register is written. The content of the Command Block registers become parameters of the command when this register is written. Writing this register clears any pending interrupt condition.

FUNCTIONAL DESCRIPTION - This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The executable commands, the command codes, and the necessary parameters for each command are listed in Table .

FIELD/BIT DESCRIPTION -

7	6	5	4	3	2	1	0
Command Code

Cylinder High register

ADDRESS - CS(1:0)=2h, DA(2:0)=5h

DIRECTION - This register is read/write.

ACCESS RESTRICTIONS - This register shall be written only when both BSY and DRQ are zero and DMARQ is not asserted. The contents of this register are valid only when both BSY and DRQ are zero. If this register is written when BSY or DRQ is set to one, the result is indeterminant. The contents of the this register and all other Command Block registers are not valid while a device is in the Sleep mode.

EFFECT - Information written to this register becomes a command parameter when subsequent commands are written to the Command register.

FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the high order bits of the starting cylinder address for any media access. If the LBA bit is set to one in the Device/Head register, this register contains Bits 23-16 of the LBA for any media access.

This register shall be updated to reflect the address of the first error when a media access command is unsuccessfully completed.

FIELD/BIT DESCRIPTION -

CHS

7	6	5	4	3	2	1	0
Cylinder(15:8)

LBA

7	6	5	4	3	2	1	0
LBA(23:16)

Cylinder Low register

ADDRESS - CS(1:0)=2h, DA(2:0)=4h

DIRECTION - This register is read/write.

EFFECT - Information written to this register becomes a command parameter when subsequent commands are written to the Command register.

FUNCTIONAL DESCRIPTION -If the LBS bit is cleared to zero in the Device/Head register, this register contains the low order bits of the starting cylinder address for any media access.If the LBA bit is set to one in the Device/Head register, this register contains Bits 15-8 of the LBA for any media access.

This register shall be updated to reflect the address of the first error when a media access command is unsuccessfully completed.

FIELD/BIT DESCRIPTION -

CHS

7	6	5	4	3	2	1	0
Cylinder(7:0)

LBA

7	6	5	4	3	2	1	0
LBA(15:8)

Data register

ADDRESS - CS(1:0)=2h, DA(2:0)=0h

DIRECTION - This register is read/write.

ACCESS RESTRICTIONS - This register shall be written and the contents shall be valid on read only when DRQ is asserted and DMARQ is not asserted. The contents of the this register and all other Command Block registers are not valid while a device is in the Sleep mode.

EFFECT -PIO out data transfers are processed by a series of reads to this register, each read transferring the data that follows the previous read. PIO in data transfers are processed by a series of writes to this register, each write transferring the data that follows the previous write. The results of a read during a PIO in or a write during a PIO out is indeterminant.

FUNCTIONAL DESCRIPTION - The data register is 16-bits wide.depending on the interface width currently selected and/or the type of data being transferred by the current command.

FIELD/BIT DESCRIPTION -

15	14	13	12	11	10	9	8
Data(15:8)

7	6	5	4	3	2	1	0
Data(7:0)

Data port

ADDRESS - None

DIRECTION - This port is read/write.

ACCESS RESTRICTIONS - This port shall be written and the contents shall be valid on read only when DMARQ is asserted.

EFFECT - DMA out data transfers are processed by a series of reads to this port, each read transferring the data that follows the previous read. DMA in data transfers are processed by a series of writes to this register, each write transferring the data that follows the previous write. The results of a read during a DMA in or a write during a DMA out is indeterminant.

FUNCTIONAL DESCRIPTION - The data port is 16-bits in width.

FIELD/BIT DESCRIPTION -

15	14	13	12	11	10	9	8
Data(15:8)

7	6	5	4	3	2	1	0
Data(7:0)

Device Control register

ADDRESS - CS(1:0)=1h, DA(2:0)=6h

DIRECTION - This register is write only. If this address is read by the host, the Alternate Status register is read.

ACCESS RESTRICTIONS - This register shall only be written when DMARQ is not asserted.

EFFECTIVENESS - the content of this register shall take effect when written.

FUNCTIONAL DESCRIPTION - This register allows a host to software reset attached devices and enable/disable interrupts.

FIELD/BIT DESCRIPTION -

7	6	5	4	3	2	1	0
r	r	r	r	r	SRST	nIEN	0

Bits 7 through 3 are reserved;

SRST is the host software reset bit. See 9.2;

nIEN is the enable bit for the device interrupt to the host. When the nIEN bit is equal to zero, and the device is selected, INTRQ shall be enabled through a tri-state buffer. When the nIEN bit is equal to one, or the device is not selected, the INTRQ signal shall be in a high impedance state;

Bit 0 shall be written with zero.

Device/Head register

ADDRESS - CS(1:0)=2h, DA(2:0)=6h

DIRECTION - This register is read/write.

ACCESS RESTRICTIONS - This register shall be written only when both BSY and DRQ are zero and DMARQ is not asserted. The contents of this register are valid only when BSY and DRQ equal zero. If this register is written when BSY or DRQ is set to one, the result is indeterminant. The contents of the this register and all other Command Block registers are not valid while a device is in the Sleep mode.

EFFECT - The DRV bit becomes becomes effective when this register is written. All other bits in this register become a command parameter when subsequent commands are written to the Command register.

FUNCTIONAL DESCRIPTION - This register selects the device, defines address translation as CHS or LBA, and provides the head address if CHS or LBA (27:24) if LBA.

FIELD/BIT DESCRIPTION -

CHS

7	6	5	4	3	2	1	0
1r	LBA	r1	DEV	HS3	HS2	HS1	HS0

LBA

7	6	5	4	3	2	1	0
r1	LBA	1r	DEV	LBA(27:24)

Bit 7 shall beis set to one for backward compatibility;

Note 4: This bit may be reclaimed for use in a future ATA standard.reserved;

LBA. When this bit is equal to zero, addressing is by CHS. When this bit is equal to one, addressing is by LBA;

Bit 5 shall beis set to one for backward compatibility;

Note 5: This bit may be reclaimed for use in a future ATA standard.

DEV is the device address. When the DEV bit is equal to zero, Device 0 is selected. When the DEV bit is equal to one, Device 1 is selected;

Bit 3-0 If LBA is equal to zero (CHS), these contain the head address of the starting CHS address. The HS3 bit is the most significant bit. If LBA is equal to one (LBA), these bits contain bits 27 through 24 of the LBA. This field shall be updated to reflect the media address of the error when a media access command is unsuccessfully completed. See 7.2.

Error register

ADDRESS - CS(1:0)=2h, DA(2:0)=1h

DIRECTION - This register is read only. If this address is written to, the Features register is written.

ACCESS RESTRICTIONS - The contents of this register shall be valid when BSY and DRQ equal zero and ERR equals one. The contents of this register shall be valid upon completion of power on or a reset. The contents of this register shall be valid at the completion of an EXECUTE DEVICE DIAGNOSTIC command. The contents of the this register and all other Command Block registers are not valid while a device is in the Sleep mode.

EFFECT - None.

FUNCTIONAL DESCRIPTION - This register contains status for the current command.

Following a power on, a reset, or completion of an EXECUTE DEVICE DIAGNOSTIC command, this register contains a diagnostic code (see 8.5).

At the completion of any command except EXECUTE DEVICE DIAGNOSTIC, the contents of this register are valid when the ERR bit is equal to one in the Status register.

FIELD/BIT DESCRIPTION -

7	6	5	4	3	2	1	0
r	UNC	MC	IDNF	MCR	ABRT	TK0NF	AMNF

Bit 7 is reserved;

UNC (Uncorrectable Data Error) indicates an uncorrectable data error has been encountered;

MC (Media Changed) is used by removable media devices and indicates that new media is available to the operating system. See 7.4;

IDNF (ID Not Found) indicates the requested sector's ID field could not be found;

MCR (Media Change Requested) is used by removable media devices and indicates that a request for media removal has been detected by the device. See Clause 7.4;

ABRT (Aborted Command) indicates the requested command has been aborted because the command code or a command parameter is invalid or some other error has occurred. The device may complete some portion of the command prior to setting ABRT and terminating the command. If the command was a data transfer command, the data transferred is indeterminant;

TK0NF (Track 0 Not Found) indicates track 0 has not been found during a RECALIBRATE command;

AMNF (Address Mark Not Found) indicates the data address mark has not been found after finding the correct ID field.

Features register

ADDRESS - CS(1:0)=2h, DA(2:0)=1h

DIRECTION - This register is write only. If this address is read by the host, the Error register is read.

ACCESS RESTRICTIONS - This register shall be written only when BSY and DRQ equal zero and DMARQ is not asserted. If this register is written when BSY or DRQ is set to one, the result is indeterminant.

EFFECT - Information written to this register becomes a command parameter when subsequent commands are written to the Command register.

FUNCTIONAL DESCRIPTION - This register is command specific.

FIELD/BIT DESCRIPTION -

7	6	5	4	3	2	1	0
Command specific

Sector Count register

ADDRESS - CS(1:0)=2h, DA(2:0)=2h

DIRECTION - This register is read/write.

EFFECT - Information written to this register becomes a command parameter when subsequent commands are written to the Command register.

FUNCTIONAL DESCRIPTION - This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the device. If the value in this register is zero, a count of 256 sectors is specified.

For media access commands that complete with an error indication in the Status register, this register contains the number of sectors which need to be transferred in order to complete the request.

The contents of this register may be redefined on some commands.

FIELD/BIT DESCRIPTION -

7	6	5	4	3	2	1	0
Sector Count

Sector Number register

ADDRESS - CS(1:0)=2h, DA(2:0)=3h

DIRECTION - This register is read/write.

EFFECT - Information written to this register becomes a command parameter when subsequent commands are written to the Command register.

FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the starting sector number for any media access. If the LBA bit is set to one in the Device/Head register, this register contains Bits 7-0 of the LBA for any media access. This register is used by some non-media access commands to pass command specific information from the host to the device, or from the device to the host.

This register shall be updated to reflect the media address of the error when a media access command is unsuccessfully completed.

FIELD/BIT DESCRIPTION -

CHS

7	6	5	4	3	2	1	0
Sector(7:0)

LBA

7	6	5	4	3	2	1	0
LBA(7:0)

Status register

ADDRESS - CS(1:0)=2h, DA(2:0)=7h

DIRECTION - This register is read only. If this address is written toto by the host, the Command register is written.

ACCESS RESTRICTIONS - The contents of this register, except for BSY, shall be ignored when BSY is set equal to one. BSY is valid at all times. The contents of the this register and all other Command Block registers are not valid while a device is in the Sleep mode.

EFFECT - Reading this register when an interrupt is pending causes the interrupt to be cleared. See 5.2.10.

FUNCTIONAL DESCRIPTION - This register contains the device status. The contents of this register are updated to reflect the current state of the device and the progress of any command being executed by the device. When the BSY bit is equal to zero, the other bits in this register are valid. When the BSY bit is equal to one, other bits in this register are not valid.

Note 6: Although host systems might be capable of generating read cycles shorter than the 400 ns specified for status update following the last command or data cycle, host implementations should wait at least 400 ns before reading the Status register to insure that the BSY bit is valid.

FIELD/BIT DESCRIPTION -

7	6	5	4	3	2	1	0
BSY	DRDY	DF	DSC	DRQ	CORR	IDX	ERR

- BSY (Busy) is set whenever the device has control of the command Block Registers. When the BSY bit is equal to one, a write to a command block register by the host shall be ignored by the device.

The device shall not change the state of the DRQ bit unless the BSY bit is equal to one. When the last block of a PIO data in command has been transferred by the host, then the DRQ bit is cleared without the BSY bit being set.

When the BSY bit equals zero, the device may only change the IDX, DRDY, DF, DSC and CORR bits in the Status register and the Data register. None of the other command block registers nor other bits within the Status register shall be changed by the device.

Note 7: Detection of Tthe assertion of the CORR bit by the device while the BSY bit is cleared to zero might not be recognized by is not certain for BIOS and drivers whichthat sample status as soon as the BSY bit is equalcleared to zero.

When writing the Command register either the BSY bit shall be set, or if the BSY bit is cleared, the DRQ bit shall be set, until command completion.

Note 8: There may be times when tThe BSY bit is set and then cleared so quickly, that the host may not be able to detect that detection of the BSY bit had been being set is not certain.

The BSY bit shall be set by the device under the following circumstances:

a) within 400 ns after either the negation of RESET- or the setting of the SRST bit in the Device Control register;

b) within 400 ns after writing the Command register if the DRQ bit is not set;

c) between blocks of a data transfer during PIO data in commands if the DRQ bit is not set;

d) after the transfer of a data block during PIO data out commands if the DRQ bit is not set;

e) during the data transfer of DMA commands if the DRQ bit is not set.

The device shall not set the BSY bit at any other time.

- DRDY (Device Ready) is set to indicate that the device is capable of accepting all command codes. This bit shall be cleared at power on. Devices that implement the power management features shall maintain the DRDY bit equal to one when they are in the Idle or Standby power modes. When the state of the DRDY bit changes, it shall not change again until after the host reads the Status register.

When the DRDY bit is equal to zero, a device responds as follows:

a) the device shall accept and attempt to execute the EXECUTE DEVICE DIAGNOSTIC and INITIALIZE DEVICE PARAMETERS commands;

b) If a device accepts commands other than EXECUTE DEVICE DIAGNOSTIC and INITIALIZE DEVICE PARAMETERS during the time the DRDY bit is equal to zero, the results are vendor specific.

- DF (Device Fault) indicates a device fault error has been detected. The internal status or internal conditions that causes this error to be indicated is vendor specific.

- DSC (Device Seek Complete) indicates that the device heads are settled over a track. When an error occurs, this bit shall not be changed until the Status register is read by the host, at which time the bit again indicates the current Seek Complete status.

- DRQ (Data Request) indicates that the device is ready to transfer a word or byte of data between the host and the device.

- CORR (Corrected Data) is used to indicate a correctable data error. The definition of what constitutes a correctable error is vendor specific. This condition does not terminate a data transfer.

- IDX (Index) is vendor specific.

- ERR (Error) indicates that an error occurred during execution of the previous command. The bits in the Error register have additional information regarding the cause of the error. Once the device has set the error bit, the device shall not change the contents of the following items until a new command has been accepted, the SRST bit is set to one or RESET- is asserted:

Addresses					Functions
CS0-	CS1-	DA2	DA1	DA0	Read (DIOR-)	Write (DIOW-)
N	N	x	x	x	Data bus high impedence	Not used
					Control block registers
N	A	0	x	x	Data bus high impedence	Not used
N	A	1	0	x	Data bus high impedence	Not used
N	A	1	1	0	Alternate Status	Device Control
N	A	1	1	1	(See note 1)	Not used
					Command block registers
A	N	0	0	0	Data	Data
A	N	0	0	1	Error	Features
A	N	0	1	0	Sector Count	Sector Count
A	N	0	1	1	Sector Number LBA (7:0) (See note 2)	Sector Number LBA (7:0) (See note 2)
A	N	1	0	0	Cylinder Low LBA (15:8) (See note 2)	Cylinder Low LBA (15:8) (See note 2)
A	N	1	0	1	Cylinder High LBA (23:16) (See note 2)	Cylinder High LBA (23:16) (See note 2)
A	N	1	1	0	Device/Head LBA (27:24) (See note 2)	Device/Head LBA (27:24)(See note 2)
A	N	1	1	1	Status	Command
A	A	x	x	x	Invalid address	Invalid address
Key: A = signal asserted, N = signal negated, x = don’t care Notes: 1 This register is obsolete. It is recommended that a device not respond to a read of this address. If a device does respond, it shall not drive the DD7 signal to prevent possible conflict with floppy disk implementations. 2 Mapping of registers in LBA translation.