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Zero A

OSU8 Microprocessor

CPU Programming

Hardware Info

Schematic

Xilinx Implementation

Address Decoder

OSU8 Core

8-Bit Data ALU

Zero A

16-Bit Addr ALU

Control State Machine

Status Bits

Operand Register

Program Counter

Stack Pointer

Full Hierarchy Index

Implementation

A Zero AND Gates

This array of AND gates is used to force the A input to zero, when the AZERO signal is asserted.

Schematic Drawing

OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/and2x8x1_a.html
Last updated: February 24, 2005
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>