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P1 Pointer Register

This is the 16-bit register that holds OSU8's P1 Pointer register. Either of two sources can load the register, depending on the state of SLEB, each of the four nibbles separately enabled by ENLB, ENLT, ENHB, and ENHT. The four separate nibble-wide load signals are required to support the 4-bit immediate load instructions, which can load the P1 register.

Schematic Drawing 2:1 Mux 2:1 Mux 2:1 Mux 2:1 Mux


OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/reg16c_p1.html
Last updated: February 24, 2005
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>