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OSU8 Microprocessor
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OSU8 Xilinx Implementation

This top-level schematic represents the OSU8 implementation in a Xilinx FPGA chip. Click on the OSU8 Core block to see the OSU8 main schematic.

Thoughout these schematics, the green blocks are links to their lower level schematics. Individual gates and flip-flops do not have schematics under them, because they are the primitive elements for Xilinx place-and-route, and for the ViewSim gate-level simulation.

Lower Schematics

Schematic Drawing OSU8 Core Address Decoder

OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
Last updated: February 24, 2005
Status: These pages are a work-in-progress
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