skip navigational linksPJRC
Shopping Cart Checkout Shipping Cost Download Website
Home MP3 Player 8051 Tools All Projects PJRC Store Site Map
You are here: OSU8 Microprocessor Schematic OSU8 Core Buffers 8-Bit, Operand Search PJRC

OSU8 Microprocessor
Overview
CPU Programming
Hardware Info
Schematic
Implementation
Download Files

Tri-State Buffer, Operand Register to 8-Bit Bus

This tri-state buffer allows the Operand Register to drive the main 8-bit data bus. The input is 4-bits, which is driven onto both the upper and lower nibbles of the 8-bit bus. This is required for the immediate load instructions, which 4-bit of data from the operand must be copied into the Accumulator, B Register, or P1 Pointer.

Schematic Drawing


OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/tbuf8g_irbt.html
Last updated: February 24, 2005
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>