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OSU8 Microprocessor
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Overview
CPU Programming
Hardware Info
Schematic
Xilinx Implementation
Address Decoder
OSU8 Core
Normal Size
Large Size
8-Bit Data ALU
16-Bit Addr ALU
Control State Machine
State Register
Bus Control
Accumulator
B Register
Status Bits
Operand Register
Program Counter
Stack Pointer
P1 Pointer
P2 Pointer
16-Bit Equals
Temp Register
8-Bit Zero
Buffers
8-Bit, ALU
8-Bit, Din
8-Bit, TMP-h
8-Bit, TMP-l
8-Bit, Operand
16-Bit, B to C
16-Bit, C to D
16-Bit, P1 A
16-Bit, P1 C
16-Bit, P2 A
16-Bit, P2 C
16-Bit, PC A
16-Bit, PC C
16-Bit, SP A
16-Bit, SP C
16-Bit, 8 to D
Full Hierarchy Index
Implementation
Download Files
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Tri-State Buffer, Operand Register to 8-Bit Bus
This tri-state buffer allows the
Operand Register to drive
the main 8-bit data bus. The input is 4-bits, which is driven onto
both the upper and lower nibbles of the 8-bit bus. This is required
for the immediate load instructions, which 4-bit of data from the
operand must be copied into the Accumulator,
B Register, or
P1 Pointer.
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