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2:1 Mux

OSU8 Microprocessor

CPU Programming

Hardware Info

Schematic

Xilinx Implementation

Address Decoder

OSU8 Core

8-Bit Data ALU

16-Bit Addr ALU

Control State Machine

Status Bits

2:1 Mux

Operand Register

Program Counter

Stack Pointer

Full Hierarchy Index

Implementation

2-input MUX

The 8-input MUX is built from seven of these 2-input MUX's

Schematic Drawing

OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/my_mux2b_mux8.html
Last updated: February 24, 2005
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>