|Shopping Cart Checkout Shipping Cost Download Website|
|You are here: 8051 Tools Development Board Old Versions Rev 1 (1992) Description|
The very old design is difficult to troubleshoot due to the use of an external 27C64 EPROM for the monitor program. We highly recommend you use the new design for any new projects.
skip to the schematic. It may be valuable to only skim this section for details about how to omit the optional chips if you're using wire wrap construction or some other technique where the connections are made manually.
This section makes frequent reference to the schematic below. Unless you are using a very large monitor, this may be a good time to print the schematic to have it handy.
The 8051 uses a multiplexed external bus. Basically, what this means is that for every memory access, the 8051 initially drives port 2 and port 0 with the 16 bit address to be read or written, ignoring the special 8 bit address MOVX instruction. Port 2 is driven with the most significant byte, and port 0 is driven with the least significant byte. To use fewer pins, port 0 is reused to communicate the data later on, so a register is required to retain the least significant byte of the address while the read or write is taking place. That is the function of the 74HC373 chip. It's 'Q' outputs together with port 2 make up the 16 bit address bus seen by the rest of the system. Pin 30, "Address Latch Enable" (ALE) tells the '373 latch when to store the least significant half of the address, but unfortunately "ALE" has nothing to do with beer in this system.
The 8051 family instruction set uses three memory spaces. There is internal RAM (128 or 256 bytes), external program memory and external data memory. The external memories can each be up to 64k. Nearly all of the 8051's instructions access the internal RAM. The MOVC instruction reads from program memory, and the MOVX instruction accesses external data memory. Of course, program fetches are read from the program memory. A common practice, which is used in this design, is to combine the two memory spaces, so that reads to either type of memory will access the same devices on the board. The 74HC08 AND gate does this. If either of the inputs to an AND gate are low, the output is low, so if either RD (data memory) or PSEN (program memory) are low to indicate a read operation, the AND gate drives the RD pin on every other chip on the board low. This way, either MOVC or MOVX will read from the same chips.
Using PAULMON, this is not really required. You may choose to leave the 8051's RD pin (pin 17) unconnected and simply connect PSEN to the RD pins of all the memory devices, so that you can omit the 74HC08. In this case, MOVX will not correctly read memory, but MOVC will still work. PAULMON uses the MOVC instruction to read external memory, except for the memory editor. If you were to do the opposite (which may seem obvious from the names) leaving PSEN unconnected, and connect every RD pin to the 8051's RD pin, then the 8051 would be unable to execute code! Many other fancy memory configurations are possible, but the combined memory space (using the AND gate) is suggested, since it's simplicity may pay off when trying to debug your code.
This is a good point to note that what makes this board an effective development system. When you download your code, using PAULMON or a similar monitor, it is written into the RAM using MOVX instructions. Since PSEN causes a read from the RAM, your code can execute from the RAM. The EPROM is unwritable, and the WR signal doesn't connect to it, so if your program crashes or doesn't jump back to the monitor, you just press the reset button and you can try again as quickly as you can edit, reassemble and download your code.
The schematic below assumes that you will not be using the built-in code memory of the 8051. The EA pin (pin 31) is tied low to force it to perform all program fetches from external memory. In this case, PAULMON (or some other monitor) must be present in the EPROM so that there will be some code that "boots" the system when you apply power or reset the system.
When the 8051 reads or writes, all of the chips get the address, data, RD*PSEN and WR signals. It is the job of the 74HC138 chip to make sure that only one chip will communicate with the 8051 at a time, and that it will be the correct one, depending on which portion of the 8051's 64k of memory is being accessed. The three input lines of this decoder are the three highest bits of the address bus, so for each 8k block of memory, one of the 8 output lines will be low and all of the others will be high. It is necessary to connect the EPROM's chip select (CS) pin 20 to Y0 (pin 15) on the '138, so that when the system is reset, the program in the EPROM will be executed. As shown, the 6264 SRAM will appear from 2000-3FFF, and the two 82C55 chips will occupy 4000-5FFF and 6000-7FFF. These 82C55 chips only have four adressable locations, which will appear repeated 2048 times in each memory range... somewhat wasteful, but more efficient use of the memory would require more circuitry.
add a little blurb about how it doesn't matter which address and data lines connect where with a RAM, but it does with ROM and peripheral chips
The MAX232 chip interfaces the TXD and RXD pins of the 8051's UART to the RS-232 serial port. Standard RS-232 uses +3V or higher for logic 1, and -3V or lower for 0, and certain input and output impedances must be provided so that any shorts in the cable won't damage the hardware. The MAX232 takes care of translating the voltage levels, and it includes a charge-pump power supply (that requires the four capacitors) to produce the RS-232 voltages while operating only from the +5 volt power supply. This chip does nothing more than translate the 0-5 volt levels used by the 8051 to the RS-232 voltage levels (and impedances); the actual UART (serial port) is built into the 8051 itself. The MAX232 is more expensive than a 1488/1489 RS232 line driver pair, but since it does not require any higher voltage power supplies, the chances for destroying chips by connecting a 12 volt supply to 5 volt chips are eliminated. Nonetheless, it's still a good idea to install a polarized connector on the board and a mating connector on the power supply, so power isn't applied backwards.
Ordinarily, a 25 pin socket (female) D-type connector is used, with "transmit" connected to pin 3 and "receive" connected to pin 2. Of course, ground should connect to pin 7. This is the DCE configuration, which is used for external modems. Using this wiring, an ordinary cable intended to connect a modem should work. It may be necessary to short pin 4 to pin 5 and pin 6 to pin 20 if the host computer requires handshaking. This design assumes your software will not support handshaking (PAULMON does not support handshaking), but the other driver/receiver pair in the MAX232 could be used to add this later.
Usually RS-232 diagrams show the DTE configuration.
The 10uF capacitor, 4.7k resistor and switch make the system's reset circuit. When power is applied to the system, no charge is assumed to be stored on the capacitor. Since the capacitor will have no voltage across it, the reset line will go to Vcc. As time passes, the resistor will "pull" the reset line to ground, by adding charge to the capacitor. The reset line also drives the reset inputs of the two 82C55 chips. Since the capacitor will charge slowly, a software delay should be added before any attempts to access the 82C55 chips are made, as they may recognize the high to low transition on the reset line at a different voltage. Though 10uF and 4.7k values are shown, similar values may be substituted. The capacitor should not be less than 4.7uF. However, using a combination of larger capacitor and resistor values can be problematic, as well as annoying since the system will not begin running for some time after reset is depressed.
The crystal shown provides the system's clock, using the built-in oscillator amplifier in the 8051. Nearly any crystal may be used if it does not exceed the maximum clock speed of the particular 8051 chip. However, many 8051 chips will not operate below 1 MHz and many that do don't support low frequency crystals using the built-in oscillator. Generally, it's a good idea to clock faster than 3 MHz, and 11.0592 MHz is a popular choice, since many 8051 chips are rated for 12 MHz, and this crystal provides high speed baud rates. Using 12 MHz, 4800 baud is the maximum before the round-off errors associated with the baud rate generator become a problem.
Though not shown explicitly on the schematic, power supply decoupling capacitors are required. The "rule of thumb" is to use one 0.1uF or larger low-inductance type capacitor (mylar ceramic, Y5P, etc) between Vcc and ground for every chip, with leads to the chip's power pins kept as short as is reasonably possible. As well, one larger tantalum or perhaps electrolytic (aluminum) capacitor should be used for every 4 chips, of course connected with the positive terminal to Vcc and the negative terminal to ground.