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The "Decimator" Chip Layout

This layout preview image is also available in medium, large, and huge sizes.

Please understand this is a VERY OLD design, from 1993. It was fabricated using a 2 micron (2000 nm) silicon process.

Files to Download

  • Magic 6.3 Layout (CMOSN rules), in ZIP or GZIP format.
  • CIF Format Layout, in ZIP or GZIP format.
  • CMOSN tech file for Magic, in ZIP or GZIP format.

These layout files are in the public domain. They may be copied and used without any restrictions. Attribution is not required.

These files are provided "as is", without warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.

Fourth Order Low-Pass Filter IC with Decimation Factor of 32 (aka "The Decimator")
Paul Stoffregen - Circuit Design, IC Layout, Spice Simulation
Shivani Gupta - Schematic Entry, Switch-Level Simulation
Srinivas Pattamatta (aka PVS) - Spice Simulation, Fiddling with CAD Software
Richard Schreier - Project Specification, Architecture Outline, Free Pizza
Last updated: February 24, 2005