FPGA Schematic, 1 June 2000
Here are the current schematics, as of Jun 1, 5:14 pm. I'm not going to
write much here explaining them, like I did on
May 28. The new circuitry allows the
microprocessor to make requests, which cause the state machine to
execute them (well, it will do that someday). The state machine is
coming along nicely... it has all the states, but only a bit of logic
is in place to make the DRAM task just do a 32 bit increment, to test
that the requests are working.
I added a number of text comments to the main schematic, which more
or less explain how it works.
State Machine Schematic
Paul's Homebrew MP3 Player, Paul Stoffregen.
Designed and constructed Winter, 2000.
Last updated: November 28, 2003
Status: More info to come... just a couple photos for now.
Questions, Comments?? <email@example.com>